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features y ideal mate for that1570 preamplifier y wide gain range: ? +13.6 to +68.6db in 1db steps, and ? +5.6db y wide supply range: 5v to 17v y wide output swing:+27dbu (17v sup.) y wide input swing: +22dbu (17v sup.) y low thd+n: 0.0003% @ 22db gain y integrated differential servo minimizes output offset y zero-crossing detector minimizes switching noise y flexible, addressable spi interface y four general-purpose digital outputs y small 7mm x 7mm qfn32 package applications y digitally controlled microphone preamplifiers y digitally-controlled instrumentation amplifiers y digitally-controlled differential amplifiers y audio mixing consoles y pc audio breakout boxes y audio distribution systems y digital audio snakes y portable audio recorders that 5171 the that5171 is a digital gain controller for low-noise, analog, differential, current-feedback audio preamplifiers such as the that 1570. when used in conjunction with an appropriate analog gain block, the 5171 can set gain to 5.6db, or any gain from 13.6db to 68.6db in 1db steps, while preserving low noise and distortion. it operates from 5v to 17v supplies, support- ing input signal levels as high as +22 dbu (at 5.6db gain, and 17v supplies) in combination with the 1570 (without an external input pad). the 5171 includes a differential servo and zero- crossing detector to minimize dc offsets and glitches (zipper noise) during gain adjustments. the 5171 is controlled via an addressable serial-peripheral interface (spi) port. four gen- eral purpose outputs (gpos) can be controlled via this interface. the gpos may be connected to input pads, analog switches, mute circuits, leds, etc. the spi bus supports read-back so that host software can verify proper operation. the 5171 was designed to mate perfectly with the that 1570 differential audio preamplifier ic. together, these two ics provide a best-of- class solution for digitally-controllable audio pre- amplifier applications. however, for designers who prefer a more customized solution, the 5171 may also be used to control a discrete preampli- fier. fabricated in a high-voltage cmos process, the 5171 integrates an astonishing amount of cir- cuitry within a very small package. it comes in a small (7x7 mm) 32-pin qfn package, making it suitable for small portable devices. description high-performance digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation document 600133 rev 04 rg1 rg2 in2 in1 scap2 scap1 sout1 sout2 sclk din dout cs gpo1 gpo2 gpo3 gpo0 rst trc agnd bsy vdd vdd dgnd dgnd figure 1. that 5171 block diagram
document 600133 rev 04 page 2 of 20 that5171 high-performance digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved. connected internally to vee. solder to pcb (optionally connect to vee) for optimal performance. pad thermal pad dc servo output 2 sout2 32 dc servo output 1 sout1 31 dc servo capacitor input 2 scap2 30 dc servo capacitor input 1 scap1 29 analog ground reference agnd 28 no connect nc 27 general purpose output 3 gpo3 26 during reset: spi address bit 2 input; during run time: general purpose output 2 gpo2 25 during reset: spi address bit 1 input; during run time: general purpose output 1 gpo1 24 during reset: spi address bit 0 input; during run time: general purpose output 0 gpo0 23 busy output (active high) bsy 22 logic positive power supply vdd 21 logic ground reference dgnd 20 serial data output dout 19 serial data input din 18 serial clock input sclk 17 chip select input (active low) cs' 16 reset input (active low) rst' 15 r/c timeout or external clock input trc 14 logic positive supply voltage vdd 13 logic ground reference dgnd 12 negative analog supply voltage vee 11 analog ground reference agnd 10 positive analog supply voltage vcc 9 no connect nc 8 no connect nc 7 attenuator network output 2 [connects to preamplifier feedback input 2 (rg2)] rg2 6 attenuator network input 2 [connects to preamplifier output 2] in2 5 attenuator network input 1 [connects to preamplifier output 1] in1 4 attenuator network output 1 [connects to preamplifier feedback 1 (rg1)] rg1 3 no connect nc 2 no connect nc 1 pin description pin name pin number table 1. pin assignments
that5171 high-performance page 3 of 20 document 600133 rev 04 digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved. specifications 1 total analog supply voltage (v cc -v ee )36 v positive analog supply voltage (v cc -a gnd ) 18 v negative analog supply voltage (v ee -a gnd ) -18 v digital supply voltage (v dd -d gnd )4.5 v analog and digital ground difference (d gnd -a gnd ) 0.3 v maximum analog voltage at in1, in2 (v iamax )v cc maximum current through v dd , d gnd 100 ma minimum analog voltage at in1, in2 (v iamin )v ee maximum digital input voltage (v idmax )v dd + 0.3 v minimum digital input voltage (v idmin )d gnd - 0.3 v storage temperature range (t stg ) -40 to +125 oc operating temperature range (t op ) -40 to +85 oc junction temperature (t jmax ) +125 oc absolute maximum ratings 2,3 parameter symbol conditions min typ max units power supply analog supply voltage v cc ; -v ee referenced to a gnd 4.75 ? 17 v digital supply voltage v dd referenced to d gnd 3.0 ? 3.6 v analog supply current i cc ; -i ee no signal ? 8.3 11 ma digital supply current i dd no signal ? 2 11 a resistor ladder characteristics (dc) gain range v cc -1.6 > v in1 >v ee +1.6 [-20 log (v in1 -v in2 )/(v rg1 -v rg2 )] v cc -1.6 > v in2 >v ee +1.6 5.6 ? 68.6 db gain step size 13.6db gain 68.6db ? 1 ? db gain error all gain settings -0.5 0.15 0.5 db r g range (resistance from in 1 to in 2 ) all gain settings 4.5 5.6~1.41k 1.69k r a , r b range (resistance from in 1 to rg 1 ) (resistance from in 2 to rg 2 ) all gain settings 2.1 2.65~7.5 9 k servo amp characteristics (dc) input offset voltage v os includes bias current effects -1.6 ? +1.6 mv power supply rejection ratio psrr v cc = -v ee ; 5v to 15v 100 115 ? db maximum output voltage v omax v cc -4.5 ?? v minimum output voltage v omin ?? v ee +4.5 v maximum output current i omax 0.85 1.0 ? ma electrical characteristics 2,4 1. all specifications are subject to change without notice. 2. unless otherwise noted, t a =25oc, v cc =+15v, v ee = -15v, v dd = +3.3v 3. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ra tings only; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impl i ed. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 4. 0 dbu = 0.775 vrms
document 600133 rev 04 page 4 of 20 that5171 high-performance digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved. parameter symbol conditions min typ max units zero-crossing detector characteristics (dc) zero-crossing detector threshold ? 5 ? mv zcd timeout t zto r t = 22m , c t = 1 nf ? 22 ? ms zcd timing capacitor c t 12 nf zcd timing resistor r t 1k 22m 100m ac characteristics thd+n (differential signal applied tof = 1 khz, gain = 21.6 db, ? 0.0003 ? % in 1 , in 2 , measured at rg 1 , rg 2 ) v in1 - v in2 = < +22 dbu maximum signal voltage at in 1 , in 2 ? v cc - 2.5 ? v minimum signal voltage at in 1 , in 2 ? v ee + 2.5 ? v maximum signal voltage at rg 1 , rg 2 ? v cc - 2.5 ? v minimum signal voltage at rg 1 , rg 2 ? v ee + 1.5 ? v digital i/o characteristics high-level input voltage v ih .7*v dd ? v dd + 0.3 v low-level input voltage v il -0.3 ? 0.3*v dd v high-level output voltage v oh i o = 4 ma .8*v dd ?? v low-level output voltage v ol i o = -4 ma . ?? 0.4 v high-level output current i oh ? 425 ma low-level output current i ol ? -4 -25 ma input leakage current i in ? 210 a serial clock (sclk) characteristics frequency f sclk 0 ? 10 mhz pulse width low t pl 40 ?? ns pulse width high t ph 40 ?? ns input timing din setup; hold time t sds , t sdh 15 ?? ns cs falling to sclk rising; t cscr sclk falling to cs inactive t cfcs 50 ?? ns cs inactive to sclk rising t cicr 100 ?? ns rst hold time t rst 50 ?? ns trc hold time t trc 50 ?? ns output timing sclk rising to d out active t crda 5?10 ns sclk falling to d out data valid t cfdo ??15 ns cs in ac tiv e t o d out hi g h im peda n ce t csz 5 ?2 0 n s electrical characteristics (con?t) 1,3,4
the that 5171 is a gain controller in the form of a digitally controlled differential attenuator; it is not an amplifier. it contains a set of precision resistors, switched by a set of cmos fet switches, configured to create a variable, switched, differential attenuation network. the network?s impedances are ideal for controlling gain in low-voltage-noise, current-feed- back instrumentation amplifiers, and are optimized for low source impedance applications. for example, when coupled with a low-noise gain stage like the that 1570, it maintains 1.5nv/ hz noise floor at 68.6db gain in the complete circuit. using the 5171 the attenuator is intended primarily for use in the feedback loop of differential current-feedback gain stages, such as the that 1570. designed spe- cifically for use in high-performance microphone pre- amplifiers, that?s engineer s paid careful attention to precision, stability, and control over the resistors and their switches, in order to maintain excellent audio performance over a wide range of gains and signal levels. figure 2 shows the analog portion of the 5171 connected to a 1570. resistors r a , r b , and r g form a differential attenuator (?u-pad?). the 1570?s differen- tial output is applied to r a and r b . the output of the attenuator, appearing across r g , is connected to the inverting differential input of the dual current- feedback amplifiers in the 1570 (the r g1 and r g2 pins). the voltage divider ratio thus controls the dif- ferential gain of the circuit. the 5171 changes the attenuator settings based on the gain command provided via the spi control interface. at minimum gain, r g is ~7.93k , while r a = r b = ~3.56k , which sets the circuit gain to +5.6db. to achieve other gains, all three resistors are varied by cmos switches in order to produce 1db gain steps from +13.6 to +68.5db. at all gains, the impedance levels are chosen to minimize noise and distortion within the circuit as a whole. table 2 lists the typical internal attenuator resis- tor values for each gain setting. table 2. internal attenuator resistor values. 63 7.5k 5.6 68.6 62 6.7k 5.6 67.6 61 6.0k 5.6 66.6 60 5.3k 5.6 65.6 59 4.7k 5.6 64.6 58 4.2k 5.6 63.6 57 3.8k 5.6 62.6 56 3.4k 5.6 61.6 55 7.5k 14 60.6 54 6.7k 14 59.6 53 6.0k 14 58.6 52 5.3k 14 57.6 51 4.7k 14 56.6 50 4.2k 14 55.6 49 3.8k 14 54.6 48 3.4k 14 53.6 47 7.5k 35 52.6 46 6.7k 35 51.6 45 6.0k 35 50.6 44 5.3k 35 49.6 43 4.7k 35 48.6 42 4.2k 35 47.6 41 3.8k 35 46.6 40 3.3k 35 45.6 39 7.5k 89 44.6 38 6.7k 89 43.6 37 5.9k 89 42.6 36 5.3k 89 41.6 35 4.7k 89 40.6 34 4.2k 89 39.6 33 3.7k 89 38.6 32 3.3k 89 37.6 31 7.4k 220 36.6 30 6.6k 220 35.6 29 5.9k 220 34.6 28 5.2k 220 33.6 27 4.6k 220 32.6 26 4.1k 220 31.6 25 3.7k 220 30.6 24 3.2k 220 29.6 23 7.2k 560 28.6 22 6.4k 560 27.6 21 5.7k 560 26.6 20 5.0k 560 25.6 19 4.5k 560 24.6 18 3.9k 560 23.6 17 3.5k 560 22.6 16 3.1k 560 21.6 15 6.8k 1.4k 20.6 14 6.0k 1.4k 19.6 13 5.3k 1.4k 18.6 12 4.6k 1.4k 17.6 11 4.0k 1.4k 16.6 10 3.5k 1.4k 15.6 9 3.1k 1.4k 14.6 8 2.7k 1.4k 13.6 0 3.6k 7.9k 5.6 ?gain? register ra, rb (ohms) rg (ohms) gain setting that5171 high-performance page 5 of 20 document 600133 rev 04 digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved. t heory of operation u2 that1570 rg1 rg2 in2 in1 u1 that5171 figure 2. analog portion of 5171 connected to a 1570.
maximizing dynamic rang e the gain (actually attenuation) settings in the 5171 were chosen after careful consideration of the dynamic range available from the 1570 and similar designs. in particular, the unusual choice of 5.6db was based on the available output headroom plus our objective to preserve as much dynamic range as possible. this led us to eschew the ?round number? of 6.0db; while the round number would make for simpler calculations, it would have compromised dynamic range by ~0.5db. we anticipate that in almost all cases, the 5171/1570 combination will be followed by one of two things. first would be an attenuator network which drops the +26.6dbu max (differential) output level (assuming 15v rails ) to one compatible with the input of an a/d converter. alternatively, there might be an attenuating differential amplifier which converts the circuit?s differential output to single- ended. in either case, nice ?round? numbers for the system gain are easily achieved by changing the ana- log attenuation in these networks. see dn140 ?input and output circuits for that preamplifier ics? for circuits and ideas. accommodating high signal levels one key objective of the 5171 design was to accommodate full professional-audio signal levels. accordingly, it is fabric ated in a high-voltage cmos process which allows operation from up to 17v analog power supplies. along with proprietary (and patent-pending) drive circuitry to the switching fets, this permits low-distortion operation at signal levels up to over +22dbu in, and nearly +27dbu out. see also dn140 for more discussion and ideas. switching noise the 5171 includes several features which mini- mize switching noise during gain changes. special (patent pending) circuitry slows down the fet gate drive to minimize charge injection. this helps sup- press clicks when changing gain. as well, the fet switches are implemented in a balanced fashion so as to maintain equal perturbation to the positive and negative sides of the balanced signal path. a built-in zero-crossing de tector can be used to restrict gain changes to times when the analog signal is very close to zero. the detector monitors the dif- ferential signal present between the in 1 and in 2 pins of the 5171. when enabled, it permits gain changes to take place only when the signal is within 5mv. a timeout (set by external components r t and c t in fig- ures 3~6) ensures that a gain change will always occur at the expiration of the timeout, in case the sig- nal has not gotten within the voltage window by that time. the period of a 20hz waveform is 50ms and thus zero-crossings will occur every 25ms. accordingly, that recommends that the timeout be set to less than or equal to 25ms in order to ensure that gain changes will be made at zero-crossings unless there is some unusual low-frequency signal present. 22ms is the time constant shown in the application sche- matics. of course, for sp ecial applications, the designer may choose to disable the zero-crossing detection and force immediate gain changes without regard to the signal condition. with the zero-crossing feature enabled, gain changes are very quiet ? barely audible when per- formed in the absence of program, and all but inau- dible with program material present. servo and dc offsets the 5171 also includes an integrated differential servo amplifier which minimizes dc offset at the out- put. practically, it is impossible to ensure that the input offset voltage of the analog gain stage is low enough to maintain low output dc offset at high gains. (for <10mv output offset, the input offset at ~60db gain would have to be under 10 v!) on the other hand, it is not too difficult to make amplifiers with under 1.5mv input offset. by using such an amplifier in feedback around the analog gain stage, it is possible to generate a correction voltage that main- tains low output offset from the circuit as a whole. the integrated differential servo amplifier has under 1.5mv input offset vo ltage. it requires two large non-polar capacitors in feedback around each half of the amp to form an integrator. the integra- tor?s input is connected to the gain stage?s output, and the integrator?s output is applied to the gain stage?s input. as the loop settles, the gain stage?s out- put will be driven to the input offset voltage of the servo. the loop time constant must be set long enough so as not to interfere with low audio- frequency signals. the combination of the input coupling capacitors (c 4 and c 5 in figures 3~6), the bias resistors for the 1570 (r 1 and r 2 ? which form a load for c 4 and c 5 ), and the servo, form a 2nd order highpass filter whose characteristics change with the gain setting. the q of this filter is hig hest at the highest gain set- ting. (at low gains, the behavior is governed almost entirely by the input coupling network and bias resis- tors, since the poles split and the one related to the servo moves very low.) assuming 1.2k for r 1 and r 2 , and 1.2m for r 7 and r 8 , we can set the highest q to be about .63 (for approximately butterworth response) if we choose c 12 and c 13 to be 1/2 the val- ues of c 4 and c 5 . we recommend a 1000:1 ratio between servo feed resistors (r 7 and r 8 ) to the analog gain stage bias resistors (r 1 and r 2 ) to minimize any noise contribu- tion from the servo amp. reducing r 7 and r 8 will lower the q, while increasing them will raise the q, proportional to the square-root of resistance. mathematically, we can express the cutoff fre- quency, f 0 , and the q as: , and f o = 1 2 1 g r 7 20k c 4 c 13 , where g is the preamp q = 1 2 f 0 1 g 20k c 13 k gain, k=1+(r 7 /r 1 ), r 1 =r 2 , r 7 =r 8 , c 4 =c 5 , c 12 =c 13 , and the source impedance is less than 1k . document 600133 rev 04 page 6 of 20 that5171 high-performance digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved.
while the servo is effective at minimizin g dc offse t at the outputs, it does require time to react. when gain is changed, particularly if a sudden large increase in gain is initiated (e.g., 5.6db to 68.6db), the servo output will not change instantaneously with the gain change. immediately after the gain increase, the servo will be supplying a dc offset appropriate for the lower gain, and the dc at the output will thus change, on a transient basis, to a higher level. as the servo acquires the new required value, the dc offset will be driven down to under 1.5mv. to minimize the sonic impact of the dc offset change, that recommends that gain be increased slowly by sending many commands to the 5171 that increase gain a few db at a time, over a second or more of total time. this replaces the one big change in dc offset with a series of much smaller ones, allowing the servo some time to settle (at least par- tially) in between each step. note that the problem is much less audible during stepwise decreases in gain, since the servo?s output is not amplified as much at the new (lower) gain as it was at the previous one. control interface the 5171 includes an addressable serial- peripheral interface (spi) port to accept external gain commands. the spi inputs accept 3.3v logic levels. the 5171 address is established during reset by resistors or other appropriate loads connected to the first three general-purpose outputs (gpos 0 through 2). during reset, these serve as inputs only for pro- gramming the device?s three- bit address. addresses from 0 through 7 (binary) are accepted. the gpo3 is reserved as an input for future applications. to ensure compatibility with future revisions of the 5171, ensure that gpo3 is tied to a logic level of 0 during reset. the spi interface may be clocked at speeds of up to 10mhz. as just mentioned, the 5171 offers four general purpose outputs (the fourth one is not used for chip addressing). these provide 3.3v logic signals to drive whatever a designer may require. that5171 high-performance page 7 of 20 document 600133 rev 04 digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved.
while the 5171 is perfectly suitable for applica- tion to discrete current-feedback differential pream- plifiers, the applications discussed herein are exclusively based on use with the companion that1570 ic. this part provides the essential low- noise, current-feedback, differential analog gain stage whose gain the 5171 can control. the circuit of figure 3 shows the most basic application of the 5171 and 1570 to form a complete low-noise microphone preamplifier. gain ranges in basic configurations the circuit of figure 3 offers differential gain that varies from 5.6 to 68.6db. there is one large ~8db step from 5.6db to 13.6db. above 13.6db, gain may be controlled in 1db steps to +68.6db. for single- ended analog outputs, the circuit of figure 3 can be followed by a differential-to-single-ended converter, as shown in figure 4. here, the differential amplifier is configured for -5.6db gain in order to minimize noise and maximize headroom at the output of the circuit. including the 5.6db attenuation in the differ- ential amplifier, the system gain can be set to 0db, or any gain from +8db to +63db in 1db steps. at minimum system gain (0db) and with 15v supply rails, the maximum (differential) input signal level is +21dbu, and the maximum (differential) out- put signal level (at the out 1 and out 2 pins of the 1570) is +26.6dbu. at maximum system gain (+63db), the maximum input signal level is -42dbu, and the maximum output signal level remains +26.6dbu. all these figures increase by a little over 1db if the circuit is run from 17v supplies. with the circuit of figure 4, the maximum input signal levels remain the same, but the (now single- ended) output levels drop by 5.6db due to the loss of the differential amplifier. when converting to single- ended signals, take care to select a low-noise opamp, and pay attention to the noise generated by the impedances. the component values shown in figure 4 will largely preserve the dynamic range of the 1570 and 5171 combination, though they do compromise noise by 1db at the lowest gain settings. for many applications, the output of the micro- phone preamplifier must drive an analog-to-digital converter. most high-performance a/d converters have differential inputs, and cannot accept differen- tial signals greater than ~+8dbu. for such applica- tions, the output of the mic preamp must be attenuated to prevent overload of the a/d converter. the circuit of figure 5 shows one typical circuit, using a simple resistive attenuator (r 9 through r 11 ). the impedance levels of the attenuator are chosen to minimize their self-generated voltage noise, and to stay within the load limits of the 1570 which drives them. figure 5 assumes that the maximum differen- tial input to the a/d converter is +8dbu. for higher document 600133 rev 04 page 8 of 20 that5171 high-performance digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved. applications u2 that 1570 servo rg1 rg2 agnd in2 in1 scap2 scap1 sout1 sout2 resistor network with fet switches control logic sclk din dout cs gpo1 gpo2 gpo3 gpo0 rst trc vcc vcc 13 15 19 18 17 16 26 25 24 23 32 31 29 30 10 6 3 11 3 2 7 13 12 10 6 15 9 14 22 21 20 12 5 4 vee vee vdd vdd dgnd dgnd bsy u1 that 5171 to: host mcu - - + + figure 3. 5171/1570 basic application circuit.
(or lower) maximum input levels, or for different supply voltages to the 1570 and 5171, scale the attenuator accordingly, keep ing its total impedance (r 9 + r 10 + r 11 ) the same. in this circuit, the noise at the a/d converter input (across r11) is -120.5dbu (in a 20khz bandwidth). this compromises the the- oretical noise floor of the 1570/5171 (at minimum gain) by about 0.65db. however, the non-zero imped- ance drive to the converter may increase distortion with high-performance converters. the impact of this impedance depends on the adc. note that one drawback of the circuit shown in figure 5 is that it offers no common-mode rejection. the 1570 has unity common-mode gain regardless of that5171 high-performance page 9 of 20 document 600133 rev 04 digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved. u2 that 1570 servo rg1 rg2 agnd scap2 scap1 sout1 sout2 resistor network with fet switches control logic sclk din dout cs gpo1 gpo2 gpo0 rst trc vcc vee vee bsy u1 that 5171 to: host mcu - - + + vdd vdd dgnd dgnd vcc gpo3 in2 in1 13 15 19 18 17 16 26 25 24 23 32 31 29 30 10 6 3 11 9 14 22 21 20 12 5 4 3 2 7 13 12 10 6 15 figure 5. 5171/1570 low-cost application for output to an a/d convertor. u2 that 1570 to subsequent analog circuitry servo rg1 rg2 agnd scap2 scap1 sout1 sout2 resistor network with fet switches control logic sclk din dout cs gpo1 gpo2 gpo0 rst trc vcc vee vee bsy u1 that 5171 to: host mcu - - + + vdd vdd dgnd dgnd vcc gpo3 in2 in1 13 15 19 18 17 16 26 25 24 23 32 31 29 30 10 6 3 11 9 14 22 21 20 12 5 4 3 2 7 13 12 10 6 15 figure 4. 5171/1570 typical application with single-ended output.
its differential g ain, as does the passive attenuator shown in figure 5. this circuit 5 relies entirely upon the a/d converter?s common-mode rejection. for better distortion performance with high- quality a/d converters, and to improve common- mode rejection, consider circuits like the one in figure 6. the active (buffered) attenuator provides differential drive to the adc, which improves per- formance. note, however, that noise in the 2114 opamps shown will compromise the performance of the 5171/1570 combination by ~3db at minimum gains, so choose the active devices for low noise as well as good audio performance. rfi protection (and common-mode rejection) the circuits of fig 3 through 6 include rfi pro- tection in two sections. small capacitors (c 1 and c 2 ) are used from the positive and negative signal inputs to chassis ground, along with a larger capacitor (c 3 ) across the two inputs. these components should be located as close as possible to the input signal con- nector, and are intended to prevent rf from entering the chassis of the device. a second rf protection network is located close to the 1570, and is intended to prevent any rf picked up inside the unit from reaching the 1570?s input, where it might be rectified and cause audio- band interference. this network consists of a pair of larger capacitors (c 6 and c 7 ) to ground and one more capacitor (c 8 ) across the two input lines. if rf is pre- vented from entering the unit, and none is generated inside the unit, then these capacitors may be omitted or reduced in value. the design of these networks was arrived at after some consideration for common-mode rejection. unbalanced capacitance from either input line (in+ or in-) to ground can unbalance common-mode sig- nals, converting them to differential signals, which will be amplified along with the desired (differential) signal. the 1570 differential amplifier in the above circuits offers gain only to differential signals: common-mode signal gain is always 0db. therefore, its common-mode rejection is equal to the differen- tial gain. so long as common-mode signals are not con- verted to differential ones, this common-mode rejec- tion will prevail. because they are relatively small, differences in the values of c 1 and c 2 are less likely to cause imbalance than the larger capacitors at c 6 and c 7 . for this reason, we recommend that capaci- tors c 6 and c 7 should be at least 5% types, in order to ensure matching between their values. note that c 3 and c 8 affect only differential signals, and thus do not affect common-mode rejection. power supply decoupling power supply decoupling is required for stability of the 1570, the servo in the 5171, and to minimize digital switching noise from propagating on the power supplies. the v cc and v ee pins should be con- nected to the same analog supply which powers the analog gain stage, while the v dd pins (13 and 21) may be powered in common with other logic circuitry (microprocessors, etc.) in the unit. document 600133 rev 04 page 10 of 20 that5171 high-performance digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved. u2 that 1570 out+ out- servo rg1 rg2 agnd scap2 scap1 sout1 sout2 resistor network with fet switches control logic sclk din dout cs gpo1 gpo2 gpo0 rst trc vcc vee vee bsy u1 that 5171 to: host mcu - - + + vdd vdd dgnd dgnd vcc gpo3 in2 in1 13 15 19 18 17 16 26 25 24 23 32 31 29 30 10 6 3 11 9 14 22 21 20 12 5 4 3 2 7 13 12 10 6 15 figure 6. 5171/1570 high-performance application for output to an a/d convertor.
that recommends one decouplin g capacitor (c 16 ) for the digital power supply, placed close to pins 20 (d gnd ) and 21 (v dd ), as these pins connect to the digital output driver bus. pins 12 (d gnd ) and pin 13 (v dd ) should be connected to pins 20 and 21, respectively, through short, low-inductance paths. a gnd and d gnd should be connected together directly under the 5171. note that the part includes back-to-back diodes limiting the maximum voltage difference between these nodes. if even on a transient basis (e.g., supply spikes) a voltage difference of over 0.5 v exists between a gnd and d gnd , large currents will flow which may damage the part. as described above (in the theory section), the integrated differential servo is required for proper operation of the system as shown in the application schematics. by using the servo amplifier in feedback, output offset can be controlled over a wide range of gains. in order to optimize settling behavior, that rec- ommends that c 12 and c 13 be approximately one-half the size of c 4 and c 5 . as well, to avoid the servo from contributing noise to the preamplifier, we recom- mend that the servo?s output be divided down by approximately 1000:1 by the combination of r 7 /r 1 and r 8 /r 2 . zero crossing detector the integrated zero-crossing detector may be enabled or disabled. (see the digital control section below for details.) when enabled, it prevents gain changes from occurring until the differential output signal waveform is within 5mv of zero. it is possible that in unusual cases where significant low-frequency material is present, the zero-crossing detector may unacceptably delay a gain change from taking place. a timeout, set by r t and c t , is provided to force a gain change to occur within r t c t ms of the time it is requested, even if zero crossing is enabled. digital control reset (rst pin) asserting the rst pin low forces all internal reg- isters to their default stat e (see register definitions in spi port section for default values after reset). this pin is typically connected to system reset or to a port on the host microcontroller. durin g reset, the 5171 reads the 3-bit spi address via the gpo[2:0] pins. these pins are typi- cally connected to pull-up and pull-down resistors to establish the chip address, and serve as general pur- pose outputs during runtime. that corporation intends to offer features in future versions of the 5171 that will be configured via a pull up resistor on gpo3. thus, gpo3 should be pulled low by a resis- tor of 100 k or less on early designs before these new features become available. busy (bsy pin) the bsy pin is asserted high when the current gain setting is not equal to the value in the gain reg- ister, i.e. when a gain update is pending a zero- crossing. this pin may be monitored by the host microcontroller (e.g. connected to an external inter- rupt pin) in order to hold off a new gain command until the previous gain command has been executed. note that in zero-crossing mode, the bsy pin goes low when a pending gain change has been made. if finer gain steps are implemented in subsequent processing (typically via dsp) this signal can be used to assist in synchronizing subsequent gain changes with those implemented by the 5171. note, of course, that latency in a/d conversion must be considered when attempting to synchronize digital with analog gain updates. gain update modes (and trc pin) the 5171 supports two gain update modes, selected by the mode bits in the control/status reg- ister (table 13), as follows. 1) immediate mode : gain updates are made immediately following a rising edge on the /cs pin. 2) zero-crossing mode: updates are made on the next output signal zero-crossing after a rising edge on the /cs pin. an rc time constant con- nected to the trc pin (r t /c t in figures 3~6) establishes a time-out period in case a zero- crossing does not occur within a desired time window. the zero-crossing time-out function operates as follows: a) c t is discharged when /cs goes low (the beginning of an spi command sequence), and is allowed to start charging when /cs goes high (the end of an spi command sequence). that5171 high-performance page 11 of 20 document 600133 rev 04 digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved. table 3. spi si g nals. spi serial data output (master-in, slave-out). dout is a tristate output. dout is tristated when cs is high. dout is msb first. output/tristate 19 dout spi serial data input (master-out, slave-in). din is msb first. input 18 din spi serial clock input. an spi master supplies this clock with frequencies up to 10mhz. data is clocked into the din pin on the rising edge of sclk. data is clocked out of dout pin on the falling edge of sclk. input 17 sclk device chip select input, active low. an spi transfer begins with a high-to-low cs transition and ends with a low-to-high cs transition. when cs is high, sclk transitions are ignored. input 16 cs function i/o pin signal
b) gain is updated on the next zero-crossin g or when the voltage on the trc pin charges to 0.7*v dd -- whichever event occurs first. the recommended time constant for r t c t is ~22ms (e.g. c t = 1nf and r t = 22m ). the choice between immediate vs zero- crossing mode depends on the application. imme- diate mode has the advantage of providing immediate gain updates with deterministic latency and the abil- ity to synchronize update s between the mic preamp and subsequent signal processing (e.g. digital inter- polation of finer steps in gain), whereas zero- crossing mode has the advantage of minimizing glitches and zipper noise. serial peripheral interface (spi) port spi signals the 5171 is a slave device on the spi bus (the microcontroller host is the master). the spi signals are listed in table 3. figure 7 and table 4 show the spi timing parameters. the spi protocol consists of 16-bit read and write commands (figure 8). in a write operation, data is clocked into the din pin, msb first, on the rising edge of sclk. in a read operation, address bits are clocked into the din pin, msb first, on the rising edge of sclk, and an 8-bit data word is clocked out of the dout pin, msb first, on the falling edge of sclk. spi command format spi read and write commands are comprised of four bitfields, shown in table 5. the 3-bit device address, a[2:0], specifies which chip on the spi bus is being targeted. the r/w bit specifies whether this command is a read (0) or write (1) operation. the 3-bit register address, r[2: 0], specifies which register within the 5171 will be read or written. the data field, d[7:0], carries data for the command. spi registers spi read and write commands access registers within the 5171. the registers and their addresses are listed in table 6. document 600133 rev 04 page 12 of 20 that5171 high-performance digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved. t1 t5 t2 t3 t11 t9 t4 t6 t10 t7 t8 sclk cs din dout figure 7. spi timing. cs sclk din dout a2 d6 d5 d4 d3 d2 d1 d0 d7 0 r0 r1 r2 a0 a1 cs sclk din dout command word - write command word - read a2 x x x x xx x x d6 d5 d4 d3 d2 d1 d0 d7 0 r0 r1 r2 a0 a1 hiz hiz figure 8. spi command word formats (read and write). ( see table 5 for definitions of bitfields. ) table 4. spi timing parameters (ns). - 100 cs inactive to sclk rising t11 20 5 cs inactive to dout tristate t10 - 50 sclk falling to cs inactive t9 15 - sclk falling to dout valid t8 10 5 sclk rising to dout out of tristate t7 - 15 din hold time t6 - 15 din setup time t5 - 50 cs setup to sck rising t4 - 40 sclk high time t3 - 40 sclk low time t2 - 100 sclk cycle time t1 max min description param. table 6. spi registers. reserved 100 ~ 111 control/status 011 gpo 010 gain 001 chip id 000 function register address: r[2:0] table 5. spi command format. (see figure 8 for timing of the bits within these fields.) data for r/w=1 this is the data to be written for r/w=0 the data is ignored d[7:0] register address specifies which register within the 5171 will be read or written by the command. r[2:0] read/write control r/w = 0 for read r/w = 1 for write r/w device address during reset the gpio[2:0] pins are read as inputs to establish the device address. a[2:0] function field
chip id register (r[2:0] = 000) the read-only chip id register identifies the chip version and revision. it consists of a 6-bit chip code and a 2-bit revision code, shown in tables 7-9. the first version of the 5171 returns hex 0x84 (chipid = binary 100001; rev 00). gain register (r[2:0] = 001) gain of the 5171 is represented by the 6-bit gain register. the value of the gain register may be 0, or any value in the range 8 to 63 (decimal) as shown in table 10. note that read-only (ro) bits must be writ- ten as zeros. the actual gain setting is 5.6db higher than the value in the gain register. values 1 to 7 are not allowe d. if an illegal value is written to the gain register, the current gain setting will not be changed and the err bit in the control/status register will be set until a valid value is written. gpo register (r[2:0] = 010) the gpo register (table 11) controls the state of the general purpose output pins. a logic 0 in any of the gpo[3:0] bits sets that port low. a logic 1 sets a port high. during reset, th e gpo pins are configured as inputs and the device address is read on gpo[2:0]. that corporation intends to offer fea- tures in future versions of the 5171 that will be con- figured via a pull up/down resistor on gpo3. to ensure compatibility with new versions of the chip, gpo3 should be pulled low with a 1-10 k resistor on designs before these new features become avail- able. after reset, the gpo p ins are configured as out- puts and are available for general use. note that reading the gpo register returns the gpo[3:0] regis- ter bits, not the logic levels of the gpo pins during reset. control/status register (r[2:0] = 011) the control/status register controls the mode of the chip and returns current chip status. durin g a write to this re g ister, the read-only bits must be written as zeros. the register fields are defined in table 12, and the bitfields are described in table 13. that5171 high-performance page 13 of 20 document 600133 rev 04 digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved. table 10. gain register. 5.6 0 reset 68.6 63 111111 67.6 62 111110 ... ... ... 14.6 9 001001 13.6 8 001000 unchanged illegal 000111 unchanged illegal 000110 unchanged illegal 000101 unchanged illegal 000100 unchanged illegal 000011 unchanged illegal 000010 unchanged illegal 000001 5.6 0 000000 actual gain (db) gain register v alue ( decimal ) gain [5:0] table 13. control/status register bits. busy 0 - not busy, the switched resistors have been updated by the value in the gain register 1 - busy, a change to the switched resis- tors is pending a zero-crossing. bsy unused reserved gain error 0 - no error 1 - error if an illegal value is written to the gain register, it is ignored and the err bit is set until a valid gain value is written. err unused reserved unused reserved unused reserved gain control mode 00 - immediate gain updates 01 - gain update on zero crossings 10 - reserved 11 - reserved mode[1:0] description bit(s) table 11. gpo register. 0 0 0 0 0 0 0 0 reset rw rw rw rw ro ro ro ro type gpo 0 gpo 1 gpo 2 gpo 3 x x x x meaning 0 1 2 3 4 5 6 7 bit # table 12. control/status register. 0 0 0 0 0 0 0 0 reset rw rw rw ro ro ro ro ro type mode 0 mode 1 rsvd rsvd rsvd err rsvd bsy meaning 0 1 2 3 4 5 6 7 bit # table 9. chip revision. revision 3 11 revision 2 10 revision 1 01 revision 0 00 chip revision rev[1:0] table 8. chip id. that5171 digital preamplifier controller 100001 chip field ch[5:0] table 7. chip id register. ro ro ro ro ro ro ro ro type rev0 rev1 ch0 ch1 ch2 ch3 ch4 ch5 meaning 0 1 2 3 4 5 6 7 bit #
using the gpos to control preamplifier functions while the general purpose outputs (gpos) can be used to control any binary state functions, they are primarily intended to be used to control analog functions associated with a preamplifier. figure 9 is a block diagram showing that 5171 gpo outputs controlling typical preamp functions such as an input pad (gpo0), mic/line switching (gpo1), signal polar- ity (gpo2), and phantom power (gpo3). there are many ways to control each of these functions, each with its own tradeoffs. see design note 140 (?input and output circuits for that preamplifier ics?) for basic circuit ideas on how to implement this control using relays. look for a forthcoming design note to offer recommendations for solid-state control over these functions. driving relays from gpos frequently, the switches which control analog functions will be relays. re lays will generally require a buffer to provide current to drive their coils with- out excessively loading the 5171. figure 10 provides examples of a discrete npn buffer suitable to drive relays, and a discrete pnp buffer suitable to drive leds from the gpo outputs. (of course, an npn could be used to light an led and a pnp to drive a relay, though the available voltage at the gpo pins may make it easier to drive a relay from an npn driver.) because the gpo pins are used as inputs for the device's spi address during reset, the choice of buffer has an influence on the address which the 5171 will assume following reset. document 600133 rev 04 page 14 of 20 that5171 high-performance digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved. 1k5 100k v relay npn from gpo typical load npn sets address to logic 0 11k5 100k 3v3 pnp from gpo typical load pnp sets address to logic 1 figure 10. output drivers polarity sets 5171 address during reset. + _ + _ figure 9. gpo outputs control preamp functions.
setting the spi address via hardware design if a hard-wired spi address is appropriate for the application, the address ma y be set by choosing the polarity of buffer. during reset, npn drivers provide the corresponding gpo with a low logic level ("0"), while pnp drivers provide a high logic ("1") condition. the difference in logic levels stems from the base- emitter junction and associated bias resistors acting as a pull-up (pnp) or pull-down (npn) on each pin in its address-setting mode (during reset). after reset, the gpo outputs are initialized to logic 0. with pnp buffers the immediate post-reset condition is on. if this is an undesirable condition the 5171 should be immediately initialized to the proper state by setting the corresponding gpo out- put to a logic 1 level. flexibility in spi address setting with a tri- state buffer figure 11 shows a circuit using a 74lv125a tri- state buffer. this offers gre ater flexibility by making the spi address independent of the load connected to the ultimate gpo outputs, shown at gpo'0~gpo'3. besides making the spi address independent of buffer polarity, the tri-state buffer increases the output drive compared to that available from the 5171. one additional benefit of the circuit shown is that during reset, the buffers prevent the address- setting resistors from tur ning on circuitry connected to the gpo' connections. during reset, the gpo out- put buffers, sections a-d, are tri-stated by their out- put enable /oe. this is accomplished by complementing the /rst line using inverter e. the 5171 spi address is se t by pull-up or pull- down resistors r0a through r2b. in the example above the address is "101b" or "5d". the value of the pull-up resistors typically range from 4.7k to 47k. add r4b to ensure future compatibility in future revisions of the 5171, that has plans to use gpo3 as an input to set alternate spi opera- tion modes. to ensure compatibility with future ver- sions of the 5171, current designs should include r3b. field programming the spi address if the spi address must be field programmable, a combination of strong pull-up and weak pull-down may be used in conjunction with switches, links, or jumpers as shown in figure 11 in the dotted box. in the above example the pull-up is 4.7k , the pull- down is 47k . that5171 high-performance page 15 of 20 document 600133 rev 04 digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved. figure 11. 5171 device addressing with buffered gpo outputs. rst r 0 a 4k7 r 0 a 4k7 r 0 b 47k r 1 b 47k r 2 b 47k r 1 a 4k7 r 2 a 4k7 r 0 b 47k r 1 b 47k r 2 b 47k r 3 b 47k r 1 a 4k7 r 2 a 4k7 74lv125a a b c gpo?0 a0 - gpo0 23 24 25 26 15 a1 - gpo1 a2 - gpo2 a3 - gpo3 3.3v 5171 gpo?1 gpo?2 gpo?3 alternative for field programming the spi address 5171 address shown as 101 b (=5 dec) d e j0 a0 3.3v address ?101 b ? (=?5 dec ?) oe j1 j2 a1 a2 r 3 b 47k a3
spi bus topologies the 5171 spi port is very flexible, supporting single-device and multiple-device applications and read-back of internal registers. figures 12 through 14 show several common conf igurations. note that the 5171 always operates as the slave device on an spi bus. the configuration of figure 13 allows read and write operations to be communicated to individual devices by addressing them individually. in order to send commands to multiple devices in parallel, see the configuration in figure 14. this configuration supports parallel write ope rations to multiple 5171s with the same chip address when their chip selects are asserted together. note that in this configuration, read operations can not be performed in parallel due to contention on dout. document 600133 rev 04 page 16 of 20 that5171 high-performance digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved. mosi miso sclk gpio host microcontroller sp i p o r t di dout sclk cs that5171 #1 spi por t di dout sclk cs that5171 #2 spi por t di dout sclk cs that5171 #3 spi por t gpio gpio mosi* miso* sclk gpio *spi terminology: host microcontroller spi port di dout sclk cs figure 14. multiple 5171 ics connected in parallel to a host microcontroller, with independent chip selects. mosi miso sclk gpio host microcontroller spi port di dout sclk cs that5171 #1 spi port di dout sclk cs that5171 #2 spi port di dout sclk cs that5171 #3 spi port figure 12. single 5171 connected to a host microcontrolle r . figure 13. multiple 5171 ics connected in parallel to a host microcontroller.
the 5171 and 1570 are intended to lay out side- by-side, with pins 1 through 4 on the 1570 facing pins 1 through 7 on the 5171. see figure 15 for a suggested layout. designers should take care to minimize capaci- tance on the rg pins, and to ensure that power sup- ply lines do not run close and/or parallel to either the input signal lines or the traces and pins connected to the rg pins. for current feedback amplifiers such as the 1570, stray capacitance to ground or power planes results in higher gains at high frequencies. as a result, mismatches in the capacitance on these two nodes will degrade common-mode performance at high frequencies. additionally, power supply lines, which often carry non-linear (e.g., half-w ave rectified) versions of the signal can magnetically and capacitively couple into the input and rg lines. this can create distortion, particularly at high gains. therefore, that recommends avoiding ground plane under the in 1 and in 2 pins and associated traces. we also recommend a symmetrical pcb lay- out to match the capacitance on these nodes. as is customary with qfn packages, we recom- mend that the metal ?slug? on the bottom of the qfn package be soldered to provide physical attachment and improve thermal performance. the qfn's ther- mal resistance with the slug soldered to the pcb is not yet determined, but will be lower than the unsol- dered resistance of 90o c/w. the slug may be left un- connected electrically, or connected to v ee . when laying out the board, we recommend fol- lowing advice offered by henry w. ott in his recent book electromagnetic compatibility engineering , published in august 2009 by wiley (isbn: 978-0- 470-18930-6). in it, mr. ott recommends laying out the digital and analog ground scheme using ground planes as if they were separate planes, but do not actually separate them in the final design. as noted earlier, all bypass capacito rs should be located very close to their respective power and ground pins. in particular, for the digital supplies, c15 should con- nect close to pins 20 and 21, with a short, low- inductance path running from pin 21 to pin 13, and another one from pin 12 to 20. a useful reference for pcb layout is the demon- stration circuit board for the 5171/1570 part pair, available from that. while the board itself is of course useful to designers, the layout and schematic are published in the data sheet which covers the board, and is available for downloading from that?s web site. that5171 high-performance page 17 of 20 document 600133 rev 04 digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved. that5171 that1570 figure 15. recommended that1570/that5171 pcb la y out ( mounted on same-side of pcb ) . pcb la y out information
the that 5171 is available in a 7mm x 7mm 32-pin qfn package. the package dimensions are shown in figure 16. pinouts are given in table 1. the 5171 is lead free and rohs compliant. mate- rial declaration data sheets on the parts are available at our web site, www.thatcorp.com or upon request. for ordering information, see table 14. document 600133 rev 04 page 18 of 20 that5171 high-performance digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved. table 14. ordering information. 5171N32-U 32 pin qfn order number package a b c d f h i j k dap 5.8mm x 5.8mm 0.228? x 0.228? e g 0 sym min mm mils a 6.90 271.65 b 6.90 271.65 c 0.85 33.46 d 0.2 7.87 e 0.65 bsc 25.59 bsc f 0.35 13.78 g 0.00 0.00 h 0.175 6.89 i 5.35 210.63 j 5.35 max min max 7.10 7.10 0.95 0.3 0.45 0.05 0.225 5.45 5.45 210.63 279.53 279.53 37.40 11.81 17.72 1.97 8.86 214.57 214.57 k c' 0.4 mm x 45 c? 15.7 mils x 45 1 1 8 9 16 17 24 25 32 bottom view top view figure 16. 7 x 7mm qfn32 package dimensions. parameter symbol conditions min typ max units package style see fig. 16 for dimensions 32 pin qfn thermal resistance ja qfn package, and thermal pad 90 oc/w not soldered to board environmental regulation compliance complies with january 27, 2003 rohs requirements soldering reflow profile jedec jesd22-a113-d (250 oc) moisture sensitivity level msl above-referenced jedec 3 soldering profile package characteristics package and soldering information
that5171 high-performance page 19 of 20 document 600133 rev 04 digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved. revision histor y ? minor typographical corrections. december 2010 2476 04 3 3 17 17 18 all revised input offset voltage specification. revised max and min output current specs. added clarification to package slug soldering text. corrected pin number in bypass cap layout text. updated thermal resistance spec. removed ?preliminary? watermark. july 2010 2442 03 12 13 corrected error in table 6 - spi registers corrected error in table 8 - chip id january 2010 2364 02 10 corrected error in figure six, input inverted . october 2009 2341 01 preliminary release september 2009 ? 00 page changes date eco revision
document 600133 rev 04 page 20 of 20 that5171 high-performance digital preamplifier controller ic that corporation; 45 sumner street; milford, ma 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation; all rights reserved. notes

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